A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use uri icon


  • We present an adder/substractor and a multiplier for single precision floating point numbers in IEEE-754 format. They are fully synthesizable hardware descriptions in VHDL that are available for general and educational use. Each one is presented in a single cycle and pipelined implementation, suitable for high speed computing, with performance comparable to other available implementations. Precision for non-denormal multiplications is under ulp and for additions in ±1 LSB. © 2004 IEEE.

Publication date

  • December 1, 2004