A statistical performance comparison of numerical integrators for the real-time simulation of the fundamental DC¿DC converter models
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Hardware-in-the-Loop is a Real-Time Simulation technique that enables safe and cost-efficient testing of system dynamics and controller performance. Despite its perceived maturity, key questions remain regarding numerical error and computational burden. Prior research challenged the widely accepted ¿rule of 100 simulation steps per switching period,¿ showing that error does not necessarily decrease at higher ratios. This study aims to provide further evidence, through a systematic statistical methodology, on whether increasing the ratio inherently improves accuracy and whether the choice of numerical integrator affects this behavior, alongside other identifiable error sources such as model complexity and converter topology. Four integration methods (Forward Euler, Heun, 2nd-order Adams¿Bashforth, and 4th-order Runge¿Kutta) were implemented on a microcontroller-based RTS platform and tested using both ideal and parasitic Buck and Boost converter models. Performance was evaluated statistically across 4200 randomized duty-cycle step changes per ratio, considering numerical error, execution time, and CPU usage. Unlike previous works, this study incorporates multiple operating points and experimental validation with real converters. Results confirm the presence of the tail effect, where error increases at higher ratios, and reveal no clear advantage among the tested methods in mitigating this phenomenon. The second-order Adams¿Bashforth method demonstrated the best efficiency, whereas Forward Euler consistently exhibited the highest error. Distinct minimal-error regions were identified for each model, confirming that higher frequency ratios do not necessarily improve numerical accuracy, in agreement with previous findings. Overall, findings indicate that model complexity has a stronger impact on RTS accuracy than execution frequency or numerical method order. © 2025
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